This book provides a comprehensive introduction to Verilog HDL and its application in digital design and synthesis. It covers the fundamental concepts and syntax of Verilog, hierarchical, gate-level, dataflow (RTL), behavioral, and switch-level modeling, as well as modules, ports, tasks, functions, and practical modeling techniques. The book also discusses timing and delay simulation, user-defined primitives, the Programming Language Interface (PLI), verification methodologies, and logic synthesis with Verilog HDL. It combines theoretical concepts with practical examples and design techniques, making it a useful reference for students, engineers, and practitioners involved in digital circuit and hardware design.

Ngôn ngữ:	eng
Tác giả:	Samir Palnitkar
Thông tin nhan đề:	Verilog HDL: A guide to digital design and synthesis
Nhà xuất bản:	Prentice Hall
Loại hình:	Giáo trình sách, tham khảo / Bộ sưu tập: Công nghệ thông tin
Mô tả vật lý:	442p.
Năm xuất bản:	2006